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'''Adaptive voltage scaling''' ('''AVS''') is a [[control theory|closed-loop]] dynamic power minimization technique that adjusts the voltage supplied to a [[computer chip]] to match the chip's power needs during operation. Many computer chips, especially those in [[mobile devices]] or [[Internet of things]] devices are constrained by the power available (for example, they are limited to the power stored in a [[electric battery|battery]]) and face varying workloads.<ref>{{Cite book |chapter-url=https://people.eecs.berkeley.edu/~bora/Conferences/2016/ESSCIRC16-2.pdf |doi=10.1109/ESSCIRC.2016.7598294 |isbn=978-1-5090-2972-3|chapter=Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC |title=ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference |pages=269–272 |year=2016 |last1=Keller |first1=Ben |last2=Cochet |first2=Martin |last3=Zimmer |first3=Brian |last4=Lee |first4=Yunsup |last5=Blagojevic |first5=Milovan |last6=Kwak |first6=Jaehwa |last7=Puggelli |first7=Alberto |last8=Bailey |first8=Stevo |last9=Chiu |first9=Pi-Feng |last10=Dabbelt |first10=Palmer |last11=Schmidt |first11=Colin |last12=Alon |first12=Elad |last13=Asanovic |first13=Krste |last14=Nikolic |first14=Borivoje |s2cid=28473665 }}</ref> In other situations a chip may be constrained by the amount of heat it is allowed to generate. In addition, individual chips can vary in their efficiency due to many factors, including minor differences in manufacturing conditions.<ref>{{Cite book |chapter-url=http://www.eece.cu.edu.eg/~hfahmy/arith_class/scale_power_future.pdf |doi=10.1109/IEDM.2005.1609253 |isbn=0-7803-9268-X|chapter=Scaling, power, and the future of CMOS |title=IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest |pages=9–15 |year=2005 |last1=Horowitz |first1=M. |last2=Alon |first2=E. |last3=Patil |first3=D. |last4=Naffziger |first4=S. |last5=Kumar |first5=R. |last6=Bernstein |first6=K. |s2cid=114793159 }}</ref> AVS allows the [[voltage]] supplied to the chip, and therefore its power consumption, to be continuously adjusted to be appropriate to the workload and the parameters of the specific chip. This is accomplished by integrating a device that monitors the performance of the chip (a hardware performance manager) into the chip, which then provides information to a power controller.<ref>{{Cite journal|last1=Kushwaha|first1=Sunita|last2=Kumar|first2=Sanjay|s2cid=29261059|date=2016|title=Energy Saving Approaches for Scheduling on Parallel Systems - A Review|journal=International Journal of Computer Applications|volume=152|issue=4|pages=38–42|doi=10.5120/ijca2016911798|doi-access=free}}</ref>  

AVS is similar in its goal to [[dynamic voltage scaling]] (DVS) and [[dynamic voltage and frequency scaling]] (DVFS). All three approaches aim to reduce power usage and heat generation.<ref name="texas2" />  However AVS adapts the voltage directly to the conditions on the chip,<ref name=":0">{{Cite journal|last1=Gupte|first1=Ajit|last2=Dwivedi|first2=Satyam|last3=Mehta|first3=Nandish|last4=Amrutur|first4=Bharadwaj|date=2011|title=Adaptative Techniques to Reduce Power in Digital Circuits|journal=Journal of Low Power Electronics and Applications|language=en|volume=1|issue=2|pages=261–276|doi=10.3390/jlpea1020261|doi-access=free}}</ref> allowing it to address [[real-time computing|real-time]] power requirements as well as chip-to-chip variations and changes in performance that occur as the chip ages. 
[[File:Dynamic power Management techniques.jpg|thumb|right|Dynamic Approaches to reduce power in digital circuits]]

== Background ==
Technological advances have enabled very powerful and versatile computing systems to be implemented on smaller chips. As this allows a larger number of functions to take place in the same area, both [[current density]] and the associated [[Dissipation|power dissipation]] become more concentrated compared to larger chips. The power consumption and thermal performance of [[Integrated circuit|integrated circuits]] has become a limiting factor for high-performance systems.<ref>{{Cite journal|last1=Nakai|first1=M.|last2=Akui|first2=S.|last3=Seno|first3=K.|last4=Meguro|first4=T.|last5=Seki|first5=T.|last6=Kondo|first6=T.|last7=Hashiguchi|first7=A.|last8=Kawahara|first8=H.|last9=Kumano|first9=K.|date=2005|title=Dynamic voltage and frequency management for a low-power embedded microprocessor|journal=IEEE Journal of Solid-State Circuits|volume=40|issue=1|pages=28–35|doi=10.1109/JSSC.2004.838021|issn=0018-9200|bibcode=2005IJSSC..40...28N|s2cid=62637419}}</ref><ref>{{Cite book|title=Low power design essentials|last=Rabaey, Jan M.|date=2009|publisher=Springer|isbn=9780387717135|location=New York|oclc=405547044}}</ref><ref name=":1">{{Cite journal|last1=Elgebaly|first1=M.|last2=Sachdev|first2=M.|date=2007|title=Variation-Aware Adaptive Voltage Scaling System|journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems|volume=15|issue=5|pages=560–571|doi=10.1109/TVLSI.2007.896909|s2cid=12638702|issn=1063-8210}}</ref> Mobile devices are also limited by the total amount of power available.<ref name=":0" /> Minimizing power consumption in digital [[CMOS]] circuits requires significant design effort at all levels. Supply voltage reduction is one way to achieve this, but static supply voltage reduction can reduce performance. [[Dynamic Voltage Scaling|Dynamic voltage scaling]] systems are used to adjust the supply voltage to the specific operations the chip is performing. However, conventional DVS systems do not directly monitor the performance of the chip and must therefore accommodate operation under worst-case performance scenarios.<ref name=":0" /> AVS aims to supply each individual domain of the system on the chip with just enough voltage to perform its task under the conditions actually experienced by the chip, minimizing power consumption per processor domain.<ref name="texas2" />

== Advantages of AVS ==
Adaptive voltage scaling is a closed-loop DVS approach that evaluates different factors, such as process variations from device to device on a chip, temperature fluctuations during chip operations, and load variations, and establishes a voltage-frequency relationship for the circuit under those conditions. Each individual chip's [[Process corners|process corner]] is determined either during manufacturing or during runtime and the optimal [[Voltage-controlled oscillator|voltage-frequency]] relationship is determined and subsequently used for voltage optimization. The advantages offered by this approach are:<ref name="texas2">{{Cite journal|title=Adaptive (Dynamic) Voltage (Frequency) Scaling—Motivation and Implementation|last=Texas Instruments — Application Report|date=March 2014|doi=10.1109/TVLSI.2007.896909|s2cid=12638702}}</ref>

*Delivery of the desired voltage to every block of the system despite variations in temperature, process corner and frequency;
*Processor- and architecture-independent implementation of power reduction; 
*Typical savings of about 55% compared to open-loop Dynamic Voltage Scaling approaches{{cn|date=April 2019}}.

Adaptive voltage scaling is used to address the energy-saving requirements of [[ASICs|application-specific integrated circuits]], [[microprocessors]] and [[System on a chip|system on a chip circuits]]. It is also well-suited for high-volume systems such as [[data centers]] and wireless base stations, as well as power-constrained applications such as portable devices, [[USB]] peripherals, and [[consumer electronics]].<ref name="texas2" />

== Comparison between DVS and AVS ==
The primary difference between DVS and AVS is that the former has an [[Control theory|open loop]] control architecture whereas the latter is [[Closed- loop|closed-loop]]. That is, in AVS there is direct [[feedback]] between the performance of the chip and the voltage provided to it. 

=== DVS ===
A generic DVS system has a performance manager, a [[phase-locked loop]] and a [[voltage regulator]].<ref name=":1" /> The performance manager uses a software interface to predict the performance requirements of the next task. Once the power requirements have been determined, the voltage and frequency are set by the performance manager. The [[phase-locked loop]] accomplishes the frequency scaling depending on the target frequency set by the performance manager. Similarly, the [[voltage regulator]] is programmed to scale the supply voltage in order to achieve the target voltage for the task. DVS systems use a one-to-one mapping of the voltage to frequency to perform the voltage scaling. Frequency-voltage pairs are determined by characterizing the chip's performance under worst-case conditions and stored in a [[lookup table]]. If conditions are more favorable, there may be a significant over-supply of power. 

=== AVS ===
In closed-loop systems such as AVS, actual on-chip conditions are measured and used to determine the target voltage and frequency.<ref name="texas2" /><ref name=":1" /> Several different implementations of AVS have been developed. 

==== Critical Path Emulation ====
[[File:Critical path monitoring technique.jpg|thumb|right|Critical Path Monitoring Technique for Adaptive Voltage Scaling]]
One way to determine the voltage-frequency relationship of the chip is to use a critical path emulator.<ref name=":1" /> The emulator is tuned during the manufacturing process to closely model the behavior of the chip, and adapts to environmental and process variations. Measuring the behavior of the emulator allows the supply voltage to be automatically adjusted such that the minimum voltage is supplied for the target task.<ref name=":0" />

A [[ring oscillator]] that operates at the same voltage as that of the rest of the chip can be used as a critical path emulator. The ring oscillator's measured frequency indicates the voltage-frequency relationship for the chip under the conditions in which it is operating.

Another type of emulator is a "delay chain" of [[inverter]]s, [[NAND gates]], wire segments, etc. The exact setting of the delay chain is determined during manufacturing after testing. The delay chain is then used to measure the time taken for a process to traverse the chain, simulating the performance of the chip.<ref name=":1" /><ref name=":2">{{Cite journal|last1=Gupte|first1=Ajit|last2=Dwivedi|first2=Satyam|last3=Mehta|first3=Nandish|last4=Amrutur|first4=Bharadwaj|date=2011|title=Adaptative Techniques to Reduce Power in Digital Circuits|journal=Journal of Low Power Electronics and Applications|language=en|volume=1|issue=2|pages=261–276|doi=10.3390/jlpea1020261|doi-access=free}}</ref><ref name=":3">{{Cite journal|last1=Chan|first1=Tuck-Boon|last2=Chan|first2=Wei-Ting Jonas|last3=Kahng|first3=Andrew B.|date=March 2013|title=Impact of Adaptive Voltage Scaling on Aging-Aware Signoff|url=https://vlsicad.ucsd.edu/Publications/Conferences/294/c294.pdf|journal=Proceedings of the Conference on Design, Automation and Test in Europe|pages=1683–1688|doi=10.7873/DATE.2013.340|isbn=9781467350716|citeseerx=10.1.1.310.2413|s2cid=140692}}</ref>

Both the ring oscillator and critical path methods suffer from the problem that they may not offer a perfect simulation of the operation of the chip, so that a safety margin must be included.<ref name=":2" />

==== Direct measurement of circuit behavior ====
An alternative to simulating the behavior of the critical path is to measure circuit performance directly. One implementation of this approach, called Razor, is based on the idea that only a subset of input patterns will activate the longest timing path on the chip.  If the voltage is too low, these input patterns will create a timing error. However, chips have error-correction systems built into them, so a low number of errors can be tolerated. The number of errors is measured and used as feedback to the power system: if the number of errors is very low, then the voltage can be dropped to save power; if the number of errors is above a certain threshold, then the voltage must be increased.<ref name=":0" /><ref name=":1" /><ref>{{Cite journal|last1=Calimera|first1=Andrea|last2=Rizzo|first2=Roberto Giorgio|date=2019|title=Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection|journal=Journal of Low Power Electronics and Applications|language=en|volume=9|issue=2|pages=17|doi=10.3390/jlpea9020017|doi-access=free}}</ref>

==== Compensation for age-related performance degradation ====
Over time, chips develop [[negative-bias temperature instability]], which increases the voltage required to operate correctly. AVS can be used to mitigate this issue by increasing the voltage to match the new requirements of the system. This is possible only if the operational degradation due to temperature instability is accurately captured by the performance sensor in the AVS system.<ref name=":3" />

==See also==
* [[power dissipation|Power Dissipation]]
* [[Low-power electronics|Low Power Electronics]]
* [[Dynamic voltage scaling|Dynamic Voltage scaling]]
* [[Negative-bias temperature instability|Bias Temperature Instability]]

==References==
{{reflist}}

[[Category:Electricity]]